| 摘要 |
A method of increasing the surface area of a STC structure, used for high density, DRAM devices, has been developed. The process consists of creating multiple, narrow crevices in a polysilicon, bottom electrode structure. This is accomplished by initially depositing a discontinuous layer of spot polysilicon on a thin silicon oxide layer, with the thin silicon oxide layer overlying the polysilicon bottom electrode. The spot polysilicon feature is transferred to the underlying thin silicon oxide layer, via conventional etching procedures, creating multiple, narrow, structures of spot polysilicon overlying the thin silicon oxide. These structures are then used as a micro-mask to create multiple, narrow crevices, via etching of the underlying polysilicon bottom electrode. Removal of the micro-mask, formation of a thin dielectric layer, and creation of a polysilicon upper electrode, complete the STC fabrication sequence.
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