Method of fabricating FET device with narrow gate length

摘要

The present invention relates to a method of forming a local threshold voltage ion implantation to reduce the junction capacitance in a semiconductor device. A polysilicon layer is formed over the device. A first dielectric layer is formed on the polysilicon layer. Then an opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a second dielectric layer is formed on the first dielectric layer. An etching step is used to formed sidewall spacers on the inner sidewalls of the opening. Then an ion implantation is performed by using said first dielectric layer and sidewall spacers as a mask.