| 摘要 |
A first phase locked loop has an oscillator operating at a first frequency and synchronized with a video signal. A counter in the first phase locked loop generates a plurality of timing signals. A second phase locked loop has an oscillator operating at a second frequency, less than the first frequency, and synchronized with a first one of the timing signals. A switch in a controller selects one of the first and second frequencies as an output. A memory for the video signal has a write clock input coupled to the slower oscillator, a read clock input coupled to the switch, and write and read reset inputs coupled respectively to second and third ones of the timing signals. The controller operates the switch responsive to an input signal. An analog to digital converter has a clamp signal input coupled to a fourth one of the timing signals.
|
