| 摘要 |
A non-volatile semiconductor memory device is provided in which a variation of threshold voltages of non-written memory cells and a potential variation of a selected bit line in preventing generation of drain disturb phenomenon are minimized Source lines SL1', SL2', SL3' and SL4' are provided in parallel to word lines WL1, WL2, WL3 and WL4, respectively, and selectively. When a data is to be written in a memory cell C11, a potential of a selected word line WL1 is set to a high voltage Vpp, potentials of non-selected word lines WL2, WL3 and WL4 are set to the drain disturb preventing voltage, for example, an intermediate voltage Vpp/2 which is a half of the high voltage. Further, a potential of a selected bit line BL1 is set to a potential Vdd which is lower than the high voltage Vpp, non-selected bit lines BL2, BL3 and BL4 are made open. Further, a potential of a selected source line SL1' is set to the ground potential GND and the non-selected source lines SL2', SL3' and SL4' are made open.
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