Method of manufacture DRAM capacitor with reduced layout area

摘要

A method of manufacturing a capacitor for use in a DRAM. The method includes forming an isolation layer over a substrate, forming a nitride layer over the isolation layer, forming a hole in the isolation and nitride layers, forming a polysilicon plug in the hole, growing an oxide plug from an upper portion of the polysilicon plug, removing the nitride layer, forming a polysilicon spacer around the oxide plug, and removing the silicon dioxide plug. Additional steps include depositing a dielectric layer onto the polysilicon sidewall and plug, and depositing a third polysilicon layer onto the dielectric layer.