| 摘要 |
<p>Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. Instead of employing passive circuit elements to interconnect the programmable logic elements (20) and the input (12) and output (15) data buses, controllable active driver circuits (52, 53) are employed. These circuits eliminate essentially all the resistance present in prior art passive connections.</p> |
