发明名称 PLL circuit
摘要 <p>PLL circuit which can be put into a locked state in a short time. The PLL circuit has a phase comparator, a loop filter and a voltage controlled oscillator. The phase comparator is provided with frequency adjusting (or matching) circuits that are operative to charge the loop filter in a case, in which it is detected that an oscillation frequency of the voltage controlled oscillator is lower than a frequency of an input signal, so as to increase the oscillation frequency of the voltage controlled oscillator until it is detected that an oscillation frequency of the voltage controlled oscillator is higher than the frequency of the input signal, and for discharging the loop filter in a case, in which it is detected that an oscillation frequency of the voltage controlled oscillator is higher than a frequency of an input signal, so as to decrease the oscillation frequency of the voltage controlled oscillator until it is detected that an oscillation frequency of the voltage controlled oscillator is lower than the frequency of the input signal. The phase comparator is further provided with phase adjusting (or matching) circuits for adjusting a phase of an output of the voltage controlled oscillator to a phase of the input signal after the oscillator frequency of the voltage controlled oscillator is adjusted to the frequency of the input sinal. Thus, a time required to adjust the oscillation frequency of the voltage controlled oscillator can be considerably reduced. &lt;IMAGE&gt;</p>
申请公布号 EP0800274(A2) 申请公布日期 1997.10.08
申请号 EP19960114005 申请日期 1996.09.02
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 YAMAGUCHI, ATSUO
分类号 H03L7/093;H03L7/08;H03L7/085;H03L7/089;H03L7/099;H03L7/113;H04L7/033;(IPC1-7):H03L7/00 主分类号 H03L7/093
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