| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce power consumption and to speed up operation by reducing the consumed current flowing in bit lines and also the loading capacity connected to the bit lines. SOLUTION: A plurality of memory cells connected to one bit line BL0 are divided to four memory blocks A-D to connect precharge transistors 5-8 to each block and to insert bus transistors 2-4 into the bit lines between each block. When the memory block C is selected by an address, the precharge transistors 5-7 of the higher-side memory blocks A, B and C, are turned off and the precharge transistor 8 of the lower-side memory block D is kept in the on-state. Further the pass transistors 2, 3 respectively inserted between the memory blocks A, B and B, C are turned on and the pass transistor 4 inserted between the lower-side memory blocks C, D is turned off to conduct the readout of data from the selected memory block C.</p> |
