发明名称 |
Method for planarizing high step-height integrated circuit structures |
摘要 |
A method for planarizing a high step-height integrated circuit structure within an integrated circuit. There is first formed upon a semiconductor substrate a high step-height integrated circuit structure. Formed then adjoining the high step-height integrated circuit structure is a patterned Global Planarization Dielectric (GPD) layer. There is then formed upon the exposed surfaces of the semiconductor substrate, the high step-height integrated circuit structure and the patterned Global Planarization Dielectric (GPD) layer a reflowable dielectric layer. Finally, the reflowable dielectric layer is reflowed.
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申请公布号 |
US5674773(A) |
申请公布日期 |
1997.10.07 |
申请号 |
US19960616897 |
申请日期 |
1996.03.15 |
申请人 |
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
KOH, CHAO-MING;LIU, BIN |
分类号 |
H01L21/3105;(IPC1-7):H01L21/70 |
主分类号 |
H01L21/3105 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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