| 摘要 |
A data demodulator demodulates a differential phase-shift-keying (DPSK) modulated receive signal to produce symbol rate demodulated data. A phase detection means, delay means, and phase difference detection means connected in cascade detect the phase of the receive signal and generate a phase difference signal having N-phases, in synchronism with respective clock signals. A decision means generates decision data on the basis of a phase range of the phase difference signal, and a decision error computing means computes a decision error on the basis of each phase of the phase difference signal and a corresponding decision phase of the decision data. Decision error adding means, and respective decision error registers accumulate and store respective decision error sums. A signal processing means reads out the decision error sum from each of the decision error registers, computes a sampling phase signal by a prescribed computing technique, and outputs a sampling phase signal. Finally, a sampling means generates the symbol rate demodulated data by sampling a phase of the decision data and the sampling phase signal.
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