发明名称 DOKIKAIRO
摘要 The invention provides a synchronous circuit which prevents occurrence of a step-out condition even when an error in padding occurs. The synchronous circuit is applied to a digital transmission system wherein the number of bits in a frame varies periodically and bit number information is included in a frame. Making use of the fact that the bit number information has a periodicity, bit number information for one period is generated by a padding bit generator (44) based on information from a synchronism detector (42) to prevent occurrence of a step-out condition caused by an error in received bit number information. <MATH>
申请公布号 JP2658896(B2) 申请公布日期 1997.09.30
申请号 JP19940209503 申请日期 1994.09.02
申请人 NIPPON DENKI KK 发明人 TAKANO HIDETO
分类号 H04J3/06;H03M7/40;H04J3/07;H04L7/08;H04N7/62;H04N19/00;H04N19/423;H04N19/65;H04N19/70 主分类号 H04J3/06
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