发明名称 |
Hardware retry trap for millicoded processor |
摘要 |
Retry trap in the processor system detects the occurrence of a hardware retry during a millicode routine. In operation, millicode resets the retry trap to "O" at the start of a millicode sequence that is sensitive to a retry operation being at some stage of the millicode sequence. The millicode routine tests the retry latch state at one or more points in the sequence to determine if a retry has occurred since the start of the sequence, which is sensitive to a retry operation. The action taken in response to a determination that a retry operation has occurred depends upon the type of potential damage to the system state as a result of the occurrence of the retry operation during the millicode sequence.
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申请公布号 |
US5673391(A) |
申请公布日期 |
1997.09.30 |
申请号 |
US19950414977 |
申请日期 |
1995.03.31 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
WEBB, CHARLES FRANKLIN;FARRELL, MARK STEVEN;SWANEY, SCOTT BARNETT |
分类号 |
G06F11/14;(IPC1-7):G06F11/34 |
主分类号 |
G06F11/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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