发明名称 Process for selective application of solder to circuit packages
摘要 Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.
申请公布号 US5672260(A) 申请公布日期 1997.09.30
申请号 US19960633322 申请日期 1996.04.17
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CAREY, CHARLES FRANCIS;FALLON, KENNETH MICHAEL;MARKOVICH, VOYA RISTA;POWELL, DOUGLAS OLIVER;VLASAK, GARY PAUL;ZARR, RICHARD STUART
分类号 C25D5/02;C25D5/08;H01L21/48;H01L21/60;H05K3/24;H05K3/34;(IPC1-7):H05K3/34 主分类号 C25D5/02
代理机构 代理人
主权项
地址