| 摘要 |
A memory cell (30) includes a ferroelectric capacitor (32) and a transistor (34) connected between one side of the capacitor and a bit line (53). A drive circuit (40) includes an operational amplifier (12) having an output, an inverting input, and a non-inverting input. A plate line (56) is connected between the other side (36) of the capacitor and the output. The non-inverting input is connected to a data-in line (47) through a first resistor (20) and to the bit line through a second resistor (21). The inverting input is connected to a constant voltage source (48) through a third resistor (22), and to the plate line (56) through a fourth resistor (23). A first buffer amplifier (82) is connected between the bit line and the second resistor, and a second buffer amplifier (84) is connected between the plate line and the fourth resistor.
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