RECEPTION DATA PROCESSING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To eliminate the fetching of erroneous data due to noise or the like generated in inserting/detaching a transmission side package by using enable signals turned significant only in a period for the valid data length of reception data and generating a latch timing. SOLUTION: A shift register 11 stores the reception data A only for the valid data length synchronized with reception clock signals C. In the meantime, a counter 12 performs a counting operation along with a decoding part 13 synchronized with the signals C only when reception enable signals B are H. The output of the counter 12 is inputted to the decoding part 13 and the decoding part 13 outputs decoding pulses E at the point of time when the counter 12 counts until the end of the reception data. The pulses E are inputted to a latch circuit 14 as latch pulses. The circuit 14 receives the pulses E, defines the rise as the latch timing e1, latches the output data D1-Dn of the shift register 11 and outputs them as parallel data F1-Fn.