发明名称 CELL MULTIPLEXING CELL BUFFER CONTROLLER
摘要 <p>PROBLEM TO BE SOLVED: To obtain cell multiplexing buffer controller where the shared buffer of an ATM multiplexing circuit is operated at high speed by applying a single port memory. SOLUTION: A part of a header part is removed by a format converting circuit 10 in an input cell. An adjusting staff byte is added. It is multiplied by the number of input ports, multiplexed in paralle conversion, alternately written in the buffer 20 with two side configuration and written in the single pot memory 30 immediately after the completion of writing for the portion of one cell. Reading from the single port memory 30 to the buffer 40 is executed by the control of a memory control circuit 70 so as to permit reading data from the single port memory by the added adjusting staff bite not to collide against writing data and transferred to the buffer 40. A parallel number converting circuit 60 executes the parallel number conversion of an output cell by inserting a removed part of the header in cell data which is read from the buffer 40.</p>
申请公布号 JPH09247175(A) 申请公布日期 1997.09.19
申请号 JP19960051787 申请日期 1996.03.08
申请人 MITSUBISHI ELECTRIC CORP 发明人 TANAKA HIROYUKI;ICHIBAGASE HIROSHI
分类号 H04Q3/00;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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