| 摘要 |
<p>The probe (10) comprises a transistor (12) of which, in use, the collector and the emitter are connected to the fault insertion point (Pi) and to a reference signal level (M; ±Vcc), respectively. The fault insertion is carried out by bringing the transistor to saturation condition. The effects of the parasitic capacitive coupling between the collector and the base of the transistor (12) are eliminated by placing, between the base and the emitter, a capacitor (19) whose capacitance is substantially higher than said parasitic capacitance. Means (20) for monitoring the current absorbed in correspondence with the fault insertion point are also provided.</p> |
