发明名称 METHOD FOR EXTRACTING GATE MODEL CIRCUIT FROM FET MODEL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten the time for extraction while keeping the coincidence of structure between two models in the method which extracts the gate model circuit from the FET model circuit. SOLUTION: This method which extracts the gate model from the FET model by using a computer-actualized expert system includes several steps. Namely, a power source, a ground and a clock signal are recognized 44, an inverter is recognized 46, and all logic signals of the FET model circuit are recognized and saved 48; and the Boolean partial trees of one or plural structure bases are assembled as to the respective recognized logic signals 50, one plural Boolean trees have branches pruned in a discovery basis 52, and a logical equation is composed from one or plural Boolean partial trees 54. The expert system device includes a FET model input net list, an inference engine, a rule base, a input, and a gate model output net list.
申请公布号 JPH09231261(A) 申请公布日期 1997.09.05
申请号 JP19960318062 申请日期 1996.11.28
申请人 HEWLETT PACKARD CO (HP) 发明人 DARIRU ARURETSUDO
分类号 G06F17/50;H03K19/00;(IPC1-7):G06F17/50 主分类号 G06F17/50
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