发明名称 CIRCUIT AND METHOD FOR VOLTAGE STRESS TEST OF WORD LINE
摘要 PROBLEM TO BE SOLVED: To improve reliability of an all word activation test in a semiconductor memory device having a word line-driving circuit, of a bootstrap method. SOLUTION: During a test, a main word line-driving voltage MWn from a main word line MWLn is once stopped to be impressed or supplied to each word line-driving circuit WDn1-WDnn in a memory array. However, complementary transistor-driving voltages Fxi, Fxi- in pairs of an Fxn driver circuit, are kept in active states VPP, Vss. Therefore, a gate node N1 in each word line-driving circuit WDn1-WDnn is charged to be at a reference level VPP-Vth via a dividing transistor Q2 while the main word line-driving voltage MWn is stopped. A predetermined time later, when the main word line-driving voltage MWn in an H level VPP is impressed, a complete self boot or bootstrap is effected because a potential of the gate node N1 sufficiently reaches the reference level VPP-Vth. A potential of a sub word line SWLn1-SWLnn is accordingly surely brought to be at the H level VPP.
申请公布号 JPH09231796(A) 申请公布日期 1997.09.05
申请号 JP19960065452 申请日期 1996.02.27
申请人 TEXAS INSTR JAPAN LTD 发明人 SUKEGAWA SHUNICHI;ABE KOICHI
分类号 G01R31/28;G01R31/30;G11C11/401;G11C11/407;G11C29/00;H01L21/66;H01L21/8242;H01L27/108 主分类号 G01R31/28
代理机构 代理人
主权项
地址