发明名称 PLL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND ATM-LAN ADAPTER CARD
摘要 PROBLEM TO BE SOLVED: To stabilize the operation of a PLL circuit. SOLUTION: The PLL circuit is formed by providing control means 63 and 64 for controlling a loop gain by changing a charge current and a discharging current for a capacitor 67 corresponding to the logical change rate of the input signal when a charge pump 235 is provided for forming an output voltage by charging and discharging the capacitor 67. Thus, when the logical change rate of the input signal is fluctuated, the PLL gain is kept constant by changing the charging current and the discharging current for the capacitor 67 at the charge pump 235 so that the operation of the PLL circuit can be stabilized.
申请公布号 JPH09232950(A) 申请公布日期 1997.09.05
申请号 JP19960062113 申请日期 1996.02.23
申请人 HITACHI LTD 发明人 NAGAYAMA YOSHIHARU
分类号 H03L7/093;H04L12/28 主分类号 H03L7/093
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