| 摘要 |
<p>An arithmetic manipulation unit (AMU) (Fig. 6) performs arithmetic operations on N-bit words in a single precision mode and on 2N-bit words in a double precision mode. Preferably, the AMU performs a double precision operation in only two pipelined cycles: a first cycle generating a first 2N-bit operand by concatenating two N-bit parts by means of a sign extension unit (42) and multiplexer (MY) (Fig. 7) and loading the operand to an output register (46); and a second cycle in which a second 2N-bit operand is generated (from a second pair of N-bit parts), the first operand is fed back from the output register, and an arithmetic operation is performed on the two operands by an arithmetic logic unit (ALU 44). A system (Fig. 1) including such an AMU circuit preferably also includes a multi-port memory (6) and a memory management unit (MMU 3; Fig. 8) using address pointers (r0-r7) to fetch two N-bit words from the memory in a single cycle.</p> |
