Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz

摘要

A process for simultaneously fabricating memory cells (2), transistors, and diodes (3) for protecting the tunnel oxide layer (9) of the cells, using the DPCC process wherein the first polysilicon layer (poly1, 10) is not removed from the transistor area, and the gate regions of the transistors are formed by shorted first (10) and second (13) polysilicon layers. To form the diodes, the poly1 layer is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping poly1; the interpoly dielectric layer (11) and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area; a second polysilicon layer (poly2) is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions (6) which, together with the substrate (4), constitute the protection diodes. The diodes are thus formed prior to shaping poly2, and are connected to the control gates (12) of the cells by the second polycrystalline silicon layer strips forming the word lines.