| 摘要 |
A memory circuit (11a) having a plurality of regions. A first rearranging circuit (12), controlled by a control circuit (14), rearranges plural bits of data having different significances when a first of the regions includes a defective portion and a first one of the plural bits is to be written into the first region, so that a second of the plural bits having lower significance than that of the first bit is written into another one of the plurality of regions. A second rearranging circuit (13), controlled by the control circuit (14), rearranges the plural bits of data read out from the memory circuit (11a) so that the first and second bits are returned to correct positions. <IMAGE> |
