发明名称 |
Process for fabricating a semiconductor integrated circuit device having the multi-layered fin structure |
摘要 |
A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-etching method using a first mask, the upper polycrystalline silicon film is patterned at first so far as to form the clearance of the upper-layer fins with the minimum working size of the memory cells of a DRAM, to form the upper-layer fin. Next, the lower-layer fin is formed by the dry-etching method using a second mask which has a pattern enlarged in self-alignment from the pattern of the first mask, so that it is given a larger horizontal size than that of the upper-layer fin.
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申请公布号 |
US5661061(A) |
申请公布日期 |
1997.08.26 |
申请号 |
US19950411149 |
申请日期 |
1995.03.27 |
申请人 |
HITACHI, LTD.;HITACHI ULSI ENGINEERING CORPORATION |
发明人 |
USUAMI, HIROHISA;TSUNOKUNI, KAZUYUKI;KOJIMA, MASAYUKI;NOJIRI, KAZUO;OKAMOTO, KEIJI |
分类号 |
H01L27/04;H01L21/822;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):H01L21/70;H01L27/00 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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