BIT SYNCHRONIZATION CIRCUIT AND BIT SYNCHRONIZATION METHOD

摘要

PROBLEM TO BE SOLVED: To provide a bit synchronization circuit for performing only correct bit synchronization without performing erroneous bit synchronization by output signals generated while being shifted from a point to perform the synchronization. SOLUTION: A means composed of flip-flops 71-79 and an exclusive OR circuit 80 inputs the polarity judged output signals 35 and level judged output signals 36 of transmission signals demodulated from binary or quaternary FSK, samples and delays the change of the polarity judged output signals and generates first sampling output 38. The means composed of the flip-flops 73-77 and an exclusive NOR circuit 81 samples and delays the change of the level judged output signals and generates second sampling output provided with prescribed time relation with the first sampling output 38. The means composed of AND circuits 82 and 83 outputs correction signals to a counter circuit when phase signals for specifying the correction range of the counter circuit and the first and second sampling output are turned to a prescribed level. Then, the clocks of the counter circuit are matched with the transmission speed of the transmission signals.