| 摘要 |
Multiplications on a finite field of cardinal 2<m> may be achieved by means of a multiplier circuit including j shift registers (R0, ..., Rj-1) into which dual-base co-ordinates of one operand are initially loaded, j being an integer greater than 1 divisor of m. The other operand is expressed in standard base. The shift registers are linked to combinatorial logics arranged to deliver the dual-base co-ordinates of the product of the two operands in m/j clock cycles, with j co-ordinates being delivered in each cycle. Multiplication execution rates may thus be increased relative to previously known dual-base multipliers that required at least m clock cycles per operation. The multiplier circuit is particularly useful in BCH decoders. |
