发明名称 |
Memory test system having a pattern generator for a multi-bit test |
摘要 |
A semiconductor memory testing methods and apparatus are arranged to accommodate a multi-bit mode of testing operation in which the memory under test itself includes internal peripheral circuits for comparing the contents of memory cells for multi-bit testing, and outputting a single-bit indicative of whether or not said multiple cells have the same state. The present invention includes methods and apparatus for determining the polarity of a memory cell under test, and taking that polarity into account informing expected data to be compared to the output of the memory under test.
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申请公布号 |
US5659549(A) |
申请公布日期 |
1997.08.19 |
申请号 |
US19960702929 |
申请日期 |
1996.08.26 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
OH, SANG-CHUL;CHO, SUNG-BUM |
分类号 |
G01R31/28;G11C29/00;G11C29/56;(IPC1-7):G06F11/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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