发明名称 |
Enhanced multiple block writes to adjacent blocks of memory using a sequential counter |
摘要 |
A memory device includes an array of randomly addressable registers. Blocks of the addressable registers are addressable by an address for block writing during a block write cycle. The blocks are of the size n, wherein n is the number of bits per plane of memory being written during the block write cycle. The device further includes a sequential counter for incrementing the address by n during burst mode when a block write is performed during a block write cycle to address a next addressable register of the array of randomly addressable registers.
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申请公布号 |
US5657287(A) |
申请公布日期 |
1997.08.12 |
申请号 |
US19950455095 |
申请日期 |
1995.05.31 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
MCLAURY, LOREN L.;MORGAN, DONALD M. |
分类号 |
G11C11/401;G11C7/10;G11C8/04;G11C8/12;G11C11/408;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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