发明名称 MANUFACTURING PROCESS FOR BORDERLESS VIAS
摘要 An improved manufacturing process and a improved device made by the process are described for forming via interconnects between metal layers in a multi-level metallization structure. An insulating cap layer (54) is deposited on the patterned and etched metal layer (6) before depositing the interlevel dielectric layer (15) above it. A two-step via etch process selectively removes portions of the cap layer (54) within vias prior to via fill.
申请公布号 WO9728563(A1) 申请公布日期 1997.08.07
申请号 WO1996US16539 申请日期 1996.10.16
申请人 ADVANCED MICRO DEVICES, INC. 发明人 MEHTA, SUNIL
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
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