| 摘要 |
A circuit for decoding one non-zero JPEG encoded pixel per clock cycle, the coded word being of variable length. For a pixel with leading zeros, a two stage pipeline is used, the first stage having one adder for calculating an delta value between the smallest number the variable length portion could be and the actual value, the second stage being an adder for adding the delta value to a base address to generate an address for a look up table, the output being the decoded value. This takes two clock periods to decode a pixel having at least one leading zero. For the Huffman code portion of encoded pixels with no leading zero's, only ten versions of which exist, a gate array for each is provided. Each detects one version and outputs the decoded Huffman code data in one clock cycle. A multiplexer then either selects the decoded data with no leading zero's in one clock cycle or the data with at least one leading zero in two clock cycles.
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