| 摘要 |
A picture element sensor circuit in an image array scanner is tested by driving a reset FET with a controllable voltage to set the reverse-bias voltage across the photo-diode at any selectable level of test voltage. In this way each pixel sensor circuit in the array may be tested as if it had received a desired amount of illumination. Alternatively, the drive voltage for the reset transistor is provided over the column output line. The controllable test voltage can be applied to the column line when no row access enable signal is applied to the array. In this situation the column line source follower circuit is inhibited by the row access FETs. Thus, a separate test voltage can be driven onto the column line, through a reset switch, and connected through the pixel sensor reset transistor to the pixel sensor photo-diode. The variable reset voltage, that is driven onto the column line, can be varied between ground and the normal bias voltage VDD for the pixel sensor by use of parallel connected P-channel FET and N-channel FET.
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