发明名称 DISPLAY DEVICE, IMAGE PROCESSOR AND ITS METHOD
摘要 PROBLEM TO BE SOLVED: To make the circuit scale small by providing an interpolation means conducting multiplication with a multiple of the n-th power of 2 with image data from an input means and addition to the data and a means displaying output image data from the interpolation means. SOLUTION: A synchronizing separator section 101 receives a video signal s101 and separates it into an image signal s102 and a synchronizing signal. A synchronizing signal measurement section 102 receives a horizontal synchronizing signal and vertical synchronizing signal cs101 and a synchronizing signal polarity discrimination signal cs102 and provides an output of the measurement result to a system control circuit 191. An interpolation processing section 105 applies vertical interpolation processing to an RGB image signal s103 obtained from an A/D converter section 103. That is, data of 1/32 to 32/32 are generated from the image data and switching of each AND gate is controlled depending on each of the data. In this embodiment, since a coefficient of the interpolation arithmetic operation is approximated by the n-th power of 2, the arithmetic operation itself is conducted by bit shift and addition 7 subtraction of data. A display section 15 displays the image signal processed by a signal processing section 14.
申请公布号 JPH09200659(A) 申请公布日期 1997.07.31
申请号 JP19960006535 申请日期 1996.01.18
申请人 CANON INC 发明人 SUGA KAZUMI
分类号 H04N5/66;G06T3/40;G09G5/00;G09G5/18;G09G5/36;(IPC1-7):H04N5/66 主分类号 H04N5/66
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