| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit with high performance suitable for circuit integration in which an unlocked state/a locked state is controlled accurately. SOLUTION: An inverter delay circuit 13 consisting of transistors(TRs) in an unlock detector 10 delays a phase lead signal PU- and a phase lag signal PD- outputted from a phase comparator 20 by a prescribed time to obtain an unlock detection signal PL, which is used to select a parameter constant of a loop filter 30 thereby controlling the unlocked state/the locked state. |
