发明名称 |
FINITE FIELD MULTIPLIER CIRCUIT AND USE THEREOF IN AN ERROR CORRECTOR DECODER |
摘要 |
Multiplications on a finite field of cardinal 2<m> may be achieved by means of a multiplier circuit including j shift registers (R0, ..., Rj-1) into which dual-base co-ordinates of one operand are initially loaded, j being an integer greater than 1 divisor of m. The other operand is expressed in standard base. The shift registers are linked to combinatorial logics arranged to deliver the dual-base co-ordinates of the product of the two operands in m/j clock cycles, with j co-ordinates being delivered in each cycle. Multiplication execution rates may thus be increased relative to previously known dual-base multipliers that required at least m clock cycles per operation. The multiplier circuit is particularly useful in BCH decoders.
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申请公布号 |
WO9727535(A1) |
申请公布日期 |
1997.07.31 |
申请号 |
WO1997FR00111 |
申请日期 |
1997.01.21 |
申请人 |
MATRA COMMUNICATION;MA, JIAN-JUN;MARCZAK, JEAN-MARC |
发明人 |
MA, JIAN-JUN;MARCZAK, JEAN-MARC |
分类号 |
G06F11/10;G06F7/72;H03M13/00;H03M13/15;(IPC1-7):G06F7/72 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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