| 摘要 |
<p>PURPOSE:To execute a data writing at a high speed in a page mode by loading an S (static) RAM for a buffer having a capacity for one page or more at the peripheral of a memory array separated from a latch circuit. CONSTITUTION:A memory array 11 is composed by matrix-arranging a NAND cell. An SRAM 20 is provided to the peripheral circuit of this array 11 separated from a latch circuit 17. For example, this SRAM 20 has the capacity of 256Xthe number 4 of the steps of the NAND cell for one page. The H L H of a writing enable signal is repeated 256X4 times with the page mode, and data for 1k are fetched in the SRAM 20. For the data fetched in the SRAM 20, the data for one page are transferred to the latch circuit 17 first. These transferred data for one page are collectively written in 256 memory cells along a word line. After that, in the same manner as above, the following data of 1k bit in the SRAM 20 are successively written continuously.</p> |
