| 摘要 |
<p>PROBLEM TO BE SOLVED: To unnecessitate the correction of the bit location for normalization and the refetching of received data. SOLUTION: A unique word detection circuit 13 compares the k-bit received data outputted from the parallel output terminals for k-bits from the (n-k+1)-th bit to the n-th-bit of the m-bit parallel output terminals of a received data shift register 12 with a k-bit unique word pattern at all times and generates an equality signal when the inputted k-bit received data is detected to be a unique word. The m-bit of the received data shift register 12 at this time is the received data of a correct bit constitution. The equality signal simultaneously resets a bit counter circuit 14 counting the bit clock for taking a slot synchronization and a slot counter circuit 15 counting a slot, respectively. The equality signal is outputted as also a reception input completion signal.</p> |
