MEMORY MODULE USING PARTIALLY DEFECTIVE MEMORY ELEMENT

摘要

PROBLEM TO BE SOLVED: To reduce the production cost by using a memory cell partly defective so as to configure a memory module. SOLUTION: 2M×8-bit 16MDRAM elements U0-U3 partially defective are mounted on a substrate 25 and pins of each memory element leading to a pin A10 are interconnected by a wire 30. The address pin A10 among address pins of the module is connected to a pad 30B and the line 30 is connected to an option pad 30A. The option pad 30A may be connected to a power terminal Vcc or to a ground terminal GND. Among 1M array of the memory elements U0-U3, in the case of the occurrence of a defect in the array whose A10 is '0', the option pad 30 is connected to the Vcc and only 1M arrays whose A10 corresponds to '1' are selected.