Structure and method for multiple-level read buffer supporting optimal throttled read operations by regulating transfer rate

摘要

A structure and a method are provided for refilling a block of memory words stored in a cache memory. The structure and method provide a read buffer to optimally match the processor speed with the main memory using read clock enable +E,ovs RdCEn+EE and acknowledge (+E,ovs Ack+EE ) signals. The +E,ovs RdCEn+EE signal is provided as each memory word is available from the main memory. The +E,ovs Ack+EE signal is provided to indicate the time at which the processor may empty the read buffer at the processor clock rate without subsequently executing a wait cycle to wait for any remaining memory words in the block to arrive. The benefit of the present invention is obtained without incurring a performance penalty on the single word read operation.