发明名称 Static timing verification in the presence of logically false paths
摘要 In a method for improving a circuit having a logically false path through static analysis of a software model, a computer receives information describing the false path, determines a true path alternate to the false path, and analyses the circuit model with respect to the true path.
申请公布号 US5648909(A) 申请公布日期 1997.07.15
申请号 US19950490439 申请日期 1995.06.12
申请人 DIGITAL EQUIPMENT CORPORATION 发明人 BIRO, LARRY L.;GRODSTEIN, JOEL J.;PAN, JENG-WEI;RETHMAN, NICHOLAS L.
分类号 G06F17/50;(IPC1-7):G06F15/00;G06G7/48 主分类号 G06F17/50
代理机构 代理人
主权项
地址