发明名称 Timing error detecting circuit
摘要 <p>A timing error detecting circuit detects a timing error of a measurement objective circuit by reading an input data in synchronism with rising or falling of a timing signal and outputting a first output data as a result of the process. The timing error detecting circuit includes a specification insertion circuit for providing an allowable specification value of a delay period relative to the timing signal, a signal processing detecting portion reading the first output data of the measurement objective circuit in synchronism with rising or falling of output of the specification insertion circuit and performing similar process to the measurement objective circuit for outputting a second output data, and a judgement circuit inputting the first and second output data of the measurement objective circuit and the signal processing detecting portion and making judgement of the timing error of the measurement objective circuit in synchronism with rising or falling of the specification insertion circuit. Thus, the timing error detecting circuit makes judgement of occurrence of timing error by the judgement circuit when a signal having the equal level to the data signal input to the measurement objective circuit is not input in synchronism with rising or falling of the output of the specification insertion circuit. &lt;IMAGE&gt;</p>
申请公布号 EP0782293(A2) 申请公布日期 1997.07.02
申请号 EP19960120201 申请日期 1996.12.16
申请人 NEC CORPORATION 发明人 ITO, HIROSHI
分类号 H03K5/00;H04L7/027;H04L7/033;(IPC1-7):H04L7/033 主分类号 H03K5/00
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