| 摘要 |
A failure memory device for compressing, in bit, failure data of a multi-bit memory under test to store the compressed failure data in a failure memory is provided, which is capable of generating a mask data. Failure data obtained from the logical comparison results of data written in a four bit memory under test are supplied to AND-OR circuits 271-274 of a compression circuit 30 through input terminals 211-214 respectively. In each AND-OR circuit, ANDs between the failure data and four bit compression data set in registers 261-264 are performed respectively, and the ANDs are ORed. The ORed outputs of the respective AND-OR circuits are supplied to input pins 221-224 of a failure memory 17. Readout data from output pins 231-234 of the failure memory are supplied to AND-OR circuits 311-314 of an expansion circuit 25 respectively. In the AND-OR circuit 311, ANDs between the read out data and the first bit data of the registers 261-264 are performed respectively and then the ANDs are ORed, and in the remaining AND-OR circuits 312-314, ANDs between the read out data and the second bit data through the fourth bit data of the registers 262-264 are performed respectively and the ANDs in each of the AND-OR circuits 312-314 are ORed. The ORed outputs of the respective AND-OR circuits are supplied to output terminals 241-244 as mask data. |
