发明名称 Method and apparatus for a single instruction multiple data early-out zero-skip multiplier
摘要 A method and apparatus for multiple parallel multiplications of multiple packed data using a single multiplier is provided. Given multiple packed data as multiplicand blocks and as multiplier blocks, an early-out zero-skip feature examines a multiplicand block to be multiplied to determine if the multiplicand block consists of all zeros. If the multiplicand block consists of all zeros, then the corresponding multiplication is skipped. The early-out zero skip multiplier also examines the most significant bits of a multiplier block to be multiplied to determine if the most significant bits consist of all zeros. If the most significant bits of the multiplier block to be multiplied consist of all zeros, then the multiplicand block is multiplied with only the least significant bits of the corresponding multiplier block. Otherwise, if the most significant bits of the multiplier block consist of both zeros and ones, then the corresponding multiplicand block is multiplied with the entire multiplier block.
申请公布号 US5642306(A) 申请公布日期 1997.06.24
申请号 US19960645633 申请日期 1996.05.15
申请人 INTEL CORPORATION 发明人 MENNEMEIER, LARRY M.;WITT, WOLF C.
分类号 G06F7/52;(IPC1-7):G06F7/52 主分类号 G06F7/52
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