| 摘要 |
PROBLEM TO BE SOLVED: To attain acceleration and miniaturization by executing an instruction in one cycle. SOLUTION: Columns 21-27 composed of NMOS transistors are provided for performing arithmetic to input lines 11a-11h and output lines 12a-12h corresponding to respective bits. The instruction is the data of seven bits and applies the data, with which only one bit turns '1' for driving the correspondent column, to shifter control lines 15a-15g. The column 21 is defined as a column for shift with which the through columns 22-27 perform the shift of prescribed bits to the side of LSB or MSB. An edge generating circuit inputs the LSB and MSB of data to be shifted and extended data and outputs the data corresponding to the instruction from an edge bit line 16 to the respective columns 22-27. Thus, when the instruction is inputted, shift processing and the processing of code extension can be simultaneously performed by the correspondent columns 22-27. |
