| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a data synchronizing system for a bus interface unit with which the flow of data is controlled between a data processor to be operated at a high clock rate and an address/data bus to be operated at a low clock rate. SOLUTION: This system incorporates four different clock areas, namely, circuit routes to be operated at a core rate, bus rate, transfer rate and reception rate, in it. The circuits for processing data only at the high clock rate of data processor 10 or only at the low clock rate of address/data bus are respectively operated in the core rate area or bus rate area. The transfer rate area is used for transferring data from the core rate to the bus rate. Inversely, the reception rate area is used for transferring data from the bus rate to the core rate.</p> |
