发明名称 DECODER SYSTEM FOR KEY FOR WRITE/ERASURE TO MEMORY CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To improve operability while preventing erroneous operations and further to decrease the number of keys to be used for memory operations. SOLUTION: This system is provided with a timer 1 for discriminating that a key is depressed continuously twice during measured time T1 and a timer 2 for discriminating that the key is depressed continuously for measured time T2, and the decode of key for write/erasure (MW/MCL) can be performed based on how many times the key for write/erasure (MW/MCL) is operated within the measured time T1 of this timer 1 and whether that key operation is performed within the measured time T2 or not. Then, a processing function for adding the change of memory contents such as write and erasure to the memory can be provided by one key for write/erasure (MW/MCL) so that operability can be improved without any confusion in key operations and the number of switches can be decreased as well.</p>
申请公布号 JPH09167043(A) 申请公布日期 1997.06.24
申请号 JP19950327276 申请日期 1995.12.15
申请人 ICOM INC 发明人 ADACHI SHINICHIRO
分类号 G06F3/02;H03M7/00;H04B1/38;(IPC1-7):G06F3/02 主分类号 G06F3/02
代理机构 代理人
主权项
地址