| 摘要 |
PROBLEM TO BE SOLVED: To reduce the time required for locking by providing a dot-lock frequency data table having different overlap rates of the retraction ranges of a PLL, performing retrieval in two stages, i.e., rough and main retrievals. SOLUTION: A display circuit part 7 is used to determine the frequency of a horizontal synchronizing signal from a terminal 1, and data is transmitted to a CPU 9, which in turn performs switching of the display circuit part 7, etc., and at the same time, transmits a signal to a clock generator 5 to control a signal from a VCO 4 so that it is converted into a required frequency for output, that is based on the determination of the horizontal frequency. From a storage part 8, the CPU 9 reads a dot-clock frequency data table in which the overlap rate of the retraction ranges of a PLL(phase-locked loop) is set to a low value, then controls the clock generator 5, reads a data table for a standard overlap rate through retraction, and determines the data for the retraction range including the frequency, thus controlling the clock generator 5. |
