发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To maintain low noise by means of a main loop with a low loop gain at the time of locking and to obtain a wide frequency acquiring band by the sub-loop of a high conversion gain controlled by a one chip microcomputer. SOLUTION: The oscillation frequency of VCO 50 is prescribedly frequency- divided by a variable frequency divider 14 and phase-compared with a H-Sync signal by a phase comparator 18. A phase comparing output is fed back to a variable capacitor Cf 54 for fine control through a charge pump 30 and LPF 34 to constitute the main loop. As one with small dC/dV is used for the variable capacitor Cf 54, the loop gain is low and the influence of noise is hardly received. On the other hand, for a variable capacitor for coarse control Cc 52, one with satisfactorily large dC/dV is used. At the time of unlocking, a microcomputer 10 changes the output of D/A converter 66. As the conversion gain of a coarse oscillation circuit is large, the oscillation frequency changes large. At the time of not being locked after waiting the acquisition time of the main loop, this processing is repeated again.
申请公布号 JPH09162730(A) 申请公布日期 1997.06.20
申请号 JP19950310241 申请日期 1995.11.29
申请人 INTERNATL BUSINESS MACH CORP (IBM) 发明人 IDEI SEIICHI;ISHIKAWA TAKUYA
分类号 H04N5/12;G09G1/16;G09G3/36;G09G5/18;H03L7/099;H03L7/10;H03L7/18 主分类号 H04N5/12
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