| 摘要 |
<p>A frequency synthesizer (100) is used for generating a plurality of signals operating at a plurality of frequencies that are integer multiples of a reference frequency. The frequency synthesizer (100) includes a plurality of phase lock loops coupled to a single phase error detector. The phase error detector (103) is connected to a reference signal (104), a first generated signal (116) and a sampler signal (136) derived from a second generated signal (132). The phase error detector (103) includes a shared counter (118), and first and second registers (106, 122) connected to the ouput of the shared counter (118). First and second phase lock loops (101, 105) are used for phase locking to the reference signal (104). The first and second phase lock loops (101, 105) derive phase error signals from the first and second registers (106, 122), thereby adjusting the first and second generated signals (116, 132).</p> |
