| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable controlling erase/erase inhibit in a line unit of each block by providing an erase-control means on each control gate line to control the application of an erase voltage which is either of a same voltage as a well- potential or a reference voltage. SOLUTION: In addition to common blocks 1 and 2, a nonvolatile semiconductor memory is provided with an erase-control circuit 3 to control an application of either of a same high voltage as a well-potential corresponding to non erasure for each of control gate lines CG11 -CG18 and CG21 -CG28 or a reference voltage 0V corresponding to erasure. And the control gate line dealing with a sensor for erasure with 0V, while the control gate line CG12 -CG17 dealing with a sector not for erasure are made to be of a same potential as a well-line W1 . Consequently, an arbitrary sector included in an erasure unit can be erased.</p> |
