| 摘要 |
The invention relates to a read-only memory cell array with a substrate (1) consisting of semiconductor material and having memory cells arranged in a cell field (5) in the region of a main surface (3). Each memory cell has at least one MOS transistor (T1, T2) with a source region (8), a drain region (17, 18), a channel region, a gate dielectric (11) and a gate electrode (13). The drain region (17, 18) is connected to a bit line (25, 29) and the gate electrode (13) to a word line (26, 27), and the MOS transistor (T1, T2) is formed by a trench (7) starting from the main surface (3) of the substrate (1) and extending to the source region (8). The invention is characterised in that the side walls (9, 10) of the trench (7) of the MOS transistor (T1, T2) are arranged at an angle of around 45 DEG to 80 DEG in relation to the main surface (3) of the substrate (1), and are doped with a doping material of a predetermined level of conductivity for establishing the programming of the MOS transistor. |
